The present invention relates generally to silicon-on-insulator (SOI) structures, and more specifically to SOI substrate structures advantageous in the fabrication of SOI transistors and bulk structures on the same substrate.
Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate and xe2x80x9coffxe2x80x9d state leakage from the drain to the source both increase power consumption. Junction capacitance also slows the speed at which a device using such transistors can operate. These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance and xe2x80x9coff statexe2x80x9d leakage problem as well as obtain reduced size, silicon-on-insulator technology (SOI) has been gaining popularity. A SOI wafer is formed from a bulk silicon wafer by using conventional oxygen implantation techniques to create a buried oxide layer at a predetermined depth below the surface. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the buried oxide layer.
One problem with forming field effect transistors on an SOI wafer is the floating body effect. The floating body effect occurs because the buried oxide layer isolates the channel, or body, of the transistor from the fixed potential silicon substrate and therefore the body takes on charge based on recent operation of the transistor. The floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate. This problem is particularly apparent for passgate devices such as those used in dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the xe2x80x9cOffxe2x80x9d position to prevent charge leakage from the storage capacitor.
Another problem associated with SOI technology is heat build up. The insulating silicon dioxide in the buried oxide layer is a poor heat conductor and prevents effective heat dissipation into bulk silicon below the buried oxide layer.
A third problem associated with SOI technology is that SOI structures are more susceptible to electrostatic damage (ESD) than bulk structures because the insulating layer inhibits use of the bulk substrate as a conductor for ESD current spikes.
Accordingly, there is a strong need in the art for a semiconductor circuit structure, and a method for forming such structure, that includes the low junction capacitance and low xe2x80x9coffxe2x80x9d state leakage characteristics of the SOI FET based circuits but does not suffer the disadvantages of a floating body potential, heat build up, and ESD fragility associated with known SOI circuits.
A first aspect of the present invention is to provide a semiconductor circuit comprising: a) a substrate having a silicon-on-insulator (SOI) region including an insulating layer of buried oxide separating a thin semiconductor device layer from a bulk silicon layer and a bulk region; and b) a logic circuit comprising an SOI circuit portion formed from SOI devices in the SOI region and a bulk circuit portion formed from bulk semiconductor structures formed in the bulk region. Further, a metal interconnect layer may operatively couple the SOI circuit portion to the bulk circuit portion.
The SOI circuit portion may include SOI FETs and the bulk circuit portion may include bulk FETs, the SOI FETs having a lower capacitance and faster operating speed than the bulk FETs. Additionally, the bulk FETs may have a larger current flow and generate more heat than the SOI FETs. The bulk circuit portion may include input/output buffer circuits and electrostatic damage (ESD) protection circuits. The ESD protection circuits may couple a plurality of controlled collapse chip connection terminals (C4 terminals) to the input/output buffer circuits. The C4 terminals may couple and bond the circuit to an IC package or a printed circuit board. A second aspect of the present invention is to provide a method of forming a silicon logic circuit comprising the steps of: a) masking a portion of the surface of a silicon substrate to form a masked region corresponding to a bulk circuit portion and an unmasked region corresponding to an SOI circuit portion; b) performing an oxygen implant to oxidize the silicon substrate to form an insulating layer of silicon dioxide beneath the unmasked region; c) forming SOI circuit structures in the SOI circuit portion and bulk circuit structures in the bulk circuit portion. Further, the method may include forming a metal interconnect layer coupling the SOI circuit structures to the bulk circuit structures.
The step of forming SOI circuit structures may include forming SOI FETs and the step of forming bulk circuit structures may include forming bulk FETs. Further, the step of forming bulk circuit structures may include forming input/output buffer circuits and ESD protection circuits. Further yet, the method may further include forming a plurality of C4 connection terminals, the ESD protection circuits coupling the connection terminals to the input/output buffer circuits.